CHERI

Capability Hardware Enhanced Risk Instructions

  • Novel ISA extension from University of Cambridge
  • Implementations for RISC-V/ARMv8/MIPS
  • Doesn’t have traditional pointers
    • Instead it has capabilities

Capabilities

128-bit datatype consisting of: 64-bit address pointer where it’s pointing Bounds - Range that pointer can point to (relative to address) Type - What it is and whether it is sealed (able to be updated) Permissions - Can you read/store/fetch this address Validity tag - Is the pointer still in use?